1. Field of the Invention
The present invention relates to a method for the manufacture of a field effect transistor which has an active layer of a gate region and ion-implanted source and drain regions formed in the main surface of a semiconductor substrate.
2. Description of the Prior Art
A Schottky junction gate type field effect transistor (hereinafter referred to as an MESFET) utilizing a compound semiconductor such as GaAs has been employed widely as a discrete semiconductor component part for a high frequency, an oscillator, and so forth; at present, it is playing an important role as a basic element of high frequency and high speed integrated circuits as well. As is well-known in the art, the high frequency performance of such an MESFET is described in the form of a ratio, Gm/Cg, where Gm and Cg are its transconductance and gate capacitance, respectively. The high frequency performance could be improved by increasing the transconductance Gm relative to the gate capacitance Cg. It is well-known that the effective transconductance Gm of the MESFET is given by Gm=Gm.sub.0 /(1+Gm.sub.0 .multidot.Rs), where Gm.sub.0 is the intrinsic transconductance dependent upon the characteristic of the channel part and Rs is the parasitic series resistance between the source and gate. As seen from the above, the presence of the parasitic series resistance Rs makes the effective transconductance Gm smaller than the intrinsic transconductance Gm.sub.0. Accordingly, how to reduce the parasitic series resistance Rs is a key for obtaining a large transconductance to improve the high frequency performance.
A known technique for diminishing the parasitic series resistance Rs is self-alignment technology for the formation of the gate-Schottky junction and the source and drain regions. This can be achieved in several ways; a typical example is shown in FIG. 9 (K. Yamasaki et al., Electron Lett. 18(3), (1982), pp 119-121). An N type impurity, for example, silicon is selectively ion implanted into the main surface of a GaAs or semi-insulating compound semiconductor substrate 11, forming therein a primary ion-implanted layer 12 which will ultimately serve as an active layer (FIG. 9A). A silicon nitride film 13 is deposited 0.15 .mu.m thick all over the main surface of the substrate 11 through plasma CVD method, for instance. Further, a resist layer 14 of a tri-level structure made up of, for example, a resist film 14.sub.1, an insulating film 14.sub.2 as of SiO.sub.2, and a resist film 14.sub.3 is formed on the silicon nitride film 13.
Next, the uppermost resist film 14.sub.3 of the tri-level resist layer 14 is patterned by photolithography, after which the intermediate insulating film 14.sub.2 and the lower most resist film 14.sub.1 are selectively removed in succession by reactive ion etching or the like using the patterned resist film 14.sub.3 as a mask, whereby apertures are made in a region where to provide the source and drain, thus partly exposing the silicon nitride film 13 through the apertures. Following this, an N type impurity, for instance, silicon, is selectively ion implanted into the substrate 11 through the tri-level resist layer 14 acting as a mask, by which is formed high impurity concentration ion-implanted layers 15 having an impurity concentration approximately 10 times higher than that of the primary ion-implanted layers 12 (FIG. 9B). Then a SiO.sub.2 film 16 is deposited, for example, 0.3 .mu.m thick over the entire area of the main surface of the substrate 11. Thereafter, the SiO.sub.2 film 16 deposited on the tri-level resist layer 14 alone is removed by a lift-off process together with the latter, leaving the SiO.sub.2 film 16 on the silicon nitride film 13 except for the portion covered with the lowermost resist film 14.sub.1 (FIG. 9C). As a result of this, the SiO.sub.2 film 16 remains unremoved almost right above each of the high impurity concentration ion-implanted layers 15. In this instance, if the tri-level resist layer 14 is selectively etched in such a T-letter shape, as a whole, that the lowermost resist film 14.sub.1 is side-etched as compared with the intermediate film 14.sub.2, as depicted in FIG. 9B, then the abovesaid SiO.sub.2 film 16 will be formed overhanging the inner end of each high impurity concentration ion-implanted layer 15 accordingly. Next, the substrate assembly is annealed, for instance, in an N.sub.2 atmosphere at 800.degree. C. for 20 minutes for activating the ion-implanted layers 15. After this, a resist pattern which has windows on positions corresponding to source and drain electrodes is formed all over the main surface of the substrate 11 with the silicon nitride film 13 and the SiO.sub.2 film 16 deposited thereon. The silicon nitride film 13 and the SiO.sub.2 16 are selectively removed by, for example, reactive ion etching and plasma etching through the resist pattern. Following this, an ohmic contact electrode material, for instance, AuGe/Ni, is vacuum evaporated through the above resist pattern and then lifted off together with the resist pattern, after which the remaining portions of the deposited metal are alloyed, providing a source electrode 17 and a drain electrode 18. Next, a resist pattern which has a window only at a position corresponding to a gate electrode is deposited all over the main surface of the substrate 11, through which pattern the silicon nitride film 13 is selectively etched away to expose the surface of the ion-implanted layer 12, through an etching process which etches the silicon nitride film 13 at a higher rate than the SiO.sub.2 film 16, such as the plasma etching or reactive ion etching process. Next, a metal which will form a Schottky junction between it and the GaAs substrate 11 is deposited on the exposed surface of the ion-implanted layer 12 and an unnecessary part of the deposited metal is lifted off together with the resist pattern, thus forming a gate electrode 19 (FIG. 9D).
The self-aligned MESFET thus obtained is, however, defective in that the gate electrode 19 overrides the insulating film 16 on either side thereof. With such a structure, the capacitance Cg between the gate electrode 19 and the channel layer is given by Cg=Cj+2Cp, i.e. the sum of the junction capacitance Cj and a parasitic capacitance Cp bwtween the electrode portion overriding the insulating layer 16 and the channel, as schematically shown in FIG. 10. In this case, an increase in the capacitance Cg will degrade the high frequency and high speed characteristics of the device, impairing the performance of the GaAs IC.